`include "defines.svh"
`include "CP0Defines.svh"
module EXT2(
    input logic [31:0]Data_From_DM,
    input logic [31:0]MEM2_ALU_Out,
    input logic [31:0]MEM2_Instr,
    output logic [31:0]Data_From_DM_AfterExt
);

always_comb begin
    unique case(MEM2_Instr[31:26])
    `lb: begin
        if(MEM2_ALU_Out[1:0] == 2'b00)
            Data_From_DM_AfterExt = {{24{Data_From_DM[7]}},Data_From_DM[7:0]};
        else if(MEM2_ALU_Out[1:0] == 2'b01)
            Data_From_DM_AfterExt = {{24{Data_From_DM[15]}},Data_From_DM[15:8]};
        else if(MEM2_ALU_Out[1:0] == 2'b10)
            Data_From_DM_AfterExt = {{24{Data_From_DM[23]}},Data_From_DM[23:16]};
        else
            Data_From_DM_AfterExt = {{24{Data_From_DM[31]}},Data_From_DM[31:24]};
    end
    `lbu: begin
        if(MEM2_ALU_Out[1:0] == 2'b00)
            Data_From_DM_AfterExt = {24'b0,Data_From_DM[7:0]};
        else if(MEM2_ALU_Out[1:0] == 2'b01)
            Data_From_DM_AfterExt = {24'b0,Data_From_DM[15:8]};
        else if(MEM2_ALU_Out[1:0] == 2'b10)
            Data_From_DM_AfterExt = {24'b0,Data_From_DM[23:16]};
        else
            Data_From_DM_AfterExt = {24'b0,Data_From_DM[31:24]};
    end
    `lh: begin
        if(MEM2_ALU_Out[1] == 1'b0)
            Data_From_DM_AfterExt = {{16{Data_From_DM[15]}},Data_From_DM[15:0]};
        else
            Data_From_DM_AfterExt = {{16{Data_From_DM[31]}},Data_From_DM[31:16]};
    end
    `lhu: begin
        if(MEM2_ALU_Out[1] == 1'b0)
            Data_From_DM_AfterExt = {16'b0,Data_From_DM[15:0]};
        else
            Data_From_DM_AfterExt = {16'b0,Data_From_DM[31:16]};
    end
    `lw: begin
        Data_From_DM_AfterExt = Data_From_DM;
    end
    default: begin
        Data_From_DM_AfterExt = 32'bx;
    end
    endcase
end

endmodule